Background description includes information that may be useful in understanding the present invention. It is not an admission that any of the information provided herein is prior art or relevant to the presently claimed invention, or that any publication specifically or implicitly referenced is prior art.
With planar bulk Metal-Oxide Semiconductor (MOS) devices reaching their scaling limits, FinFETs, Trigate, and similar non-planar technologies have become popular in recent days for use in technologies for sub-14 nm gate lengths. These technologies are found to be promising for System on Chip (SoC) applications that need reduced system cost, size, and power while enjoying improved system performance. A SoC chip in advanced CMOS consists of various analog, RF, and digital functional blocks, each of which requires dedicated ESD protection. SCRs, for example, are a must for Electrostatic Discharge (ESD) protection in low voltage-high speed I/O as well as for ESD protection of RF pads due to least parasitic loading and smallest foot print offered by SCRs. Existing SCRs suffer from very high turn-on and holding voltage, which issue becomes even severe in non-planar technologies and cannot be handled by conventional approaches such as diode- or transient-turn-on techniques.
Although the advent of non-planar technologies has paved new and efficient ways to replace their planar counterparts by offering beneficial technological solutions to scale conventional transistors, this has come with a price of lowered ESD robustness in these advanced technology nodes. ESD is a random event that leads to massive flow of current (in amperes) between bodies having different electrostatic potential for sub-500 ns duration. Such high current injection can cause severe device damage by gate oxide breakdown or meltdown of device active area. Therefore, it is important to design effective ESD protection solutions in non-planar technology nodes.
As planar bulk MOS devices reach their scaling limits, FinFETs, Trigate and similar non-planar technologies have become popular in the recent times as technology options for sub 14 nm gate lengths. These technologies are also a promising option for System on Chip (SoC) applications, where key requirements are reduced system cost, size and power while enjoying improved system performance. FinFET, also known as Fin Field Effect Transistor, is a type of non-planar or “3D” transistor used in the design of modern processors. Although providing excellent electrostatic advantages, FinFETs and other non-planar architectures suffer from lowered ESD robustness. In the last about a decade, there have been extensive investigations on designing several ESD protection concepts like Diodes, Bipolar Junction Transistors (BJTs), Metal-oxide-semiconductor field effect transistors (MOSFETs) and SCRs in FinFET technology. FinFET technology may also be used for SoC (System on chip) devices now in great demand in the ULSI industry. A SoC chip consists of various analog, RF and digital functional blocks, each requiring dedicated ESD protection concepts.
Several other prior arts, for example Russ et. al. US2004/0207021 A1, Russ et. al. U.S. Pat. No. 6,909,149 B2. Jozwiak, et al. US2005/0212051 A1, Gauthier: US2009/0206367 A1, Harald Gossner: U.S. Pat. No. 7,638,370B2, Mayank Shrivastava: US 2010/0207161 A1, James P. Di Sarro: U.S. Pat. No. 9,240,471B2 and John B. Campi: U.S. Pat. No. 9,236,374B2, Andrew Horch: U.S. Pat. No. 7,135,745B1, Mayank Shrivastava: U.S. Pat. No. 8,963,201B2 and Mayank Shrivastava: US2014/0097465A1 demonstrate various ways of implementing SCR-like devices in planar SOI and FinFET technologies with a weak tuning capability of holding and trigger voltage. However, they still do not provide a robust tuning capability or low trigger/holding voltage.
Hence, it is of crucial importance to design effective ESD protection solutions in non-planar technologies. Solutions proposed should have low turn-on and holding voltage for efficient and robust ESD protection.
All publications herein are incorporated by reference to the same extent as if each individual publication or patent application were specifically and individually indicated to be incorporated by reference. Where a definition or use of a term in an incorporated reference is inconsistent or contrary to the definition of that term provided herein, the definition of that term provided herein applies and the definition of that term in the reference does not apply.
In some embodiments, the numerical parameters set forth in the written description and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by a particular embodiment. In some embodiments, the numerical parameters should be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Notwithstanding that the numerical ranges and parameters setting forth the broad scope of some embodiments of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as practicable. The numerical values presented in some embodiments of the invention may contain certain errors necessarily resulting from the standard deviation found in their respective testing measurements.
As used in the description herein and throughout the claims that follow, the meaning of “a,” “an,” and “the” includes plural reference unless the context clearly dictates otherwise. Also, as used in the description herein, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
The recitation of ranges of values herein is merely intended to serve as a shorthand method of referring individually to each separate value falling within the range. Unless otherwise indicated herein, each individual value is incorporated into the specification as if it were individually recited herein. All methods described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples, or exemplary language (e.g. “such as”) provided with respect to certain embodiments herein is intended merely to better illuminate the invention and does not pose a limitation on the scope of the invention otherwise claimed. No language in the specification should be construed as indicating any non-claimed element essential to the practice of the invention.
Groupings of alternative elements or embodiments of the invention disclosed herein are not to be construed as limitations. Each group member can be referred to and claimed individually or in any combination with other members of the group or other elements found herein. One or more members of a group can be included in, or deleted from, a group for reasons of convenience and/or patentability. When any such inclusion or deletion occurs, the specification is herein deemed to contain the group as modified thus fulfilling the written description of all groups used in the appended claims.